Skip to main content

A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost


Volume 7 Issue 1 December - February 2019
Research Paper
Gopi Chand Naguboina*, T. Sravya**
* Assistant Professor, Department of Electronics and Communication Engineering, MaharajVijayaramGajapathi Raj (MVGR) College of Engineering (Autonomous), Vizianagaram, Andhra Pradesh, India.
** PG Scholar, Department of Electrical and Electronics Engineering, Sri PadmavatiMahilaVisvavidyalayam, Tirupati, Andhra Pradesh, India.
Naguboina, G. C., and Sravya, T. (2019). Transient Dynamic Finite Element Analysis of Cup Drawing Process. i-manager's Journal on Circuits and Systems , 7(1), 37-50. https://doi.org/10.26634/jcir.7.1.15243
Abstract
Reversible Logic is the dominating field of research in low power VLSI. In recent times, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to give an overall summary report on Digital sequential circuits like Shift registers and Counters designed using reversible logical computation. Digital circuits are the circuits implemented using Boolean logical expressions. Digital circuits find many applications in present daily life. Different types of combinational and sequential circuits are designed using reversible logic to reduce power dissipation. A Boolean function f(i1, i2, i3,……, in) having 'n' inputs and 'm' outputs is said to be logically reversible if the number of inputs are equal to the number of outputs (i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate, etc. The reversible gate must run both forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI, etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. Till date in the literature, universal shift register and shift counters are realized using reversible logical computation for the first time in this paper. In this paper, a summary report is given on Sequential circuits like Shift registers and Counters designed using reversible logical computation with improved quantum cost. A comparative study on reversible and irreversible sequential logical circuits is also given. The realized reversible logical circuits are analysed in terms of quantum cost, garbage outputs, number of gates, and propagation delay. The circuits have been designed and simulated using Xilinx software.

Comments

Popular posts from this blog

Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level

Volume 1 Issue 2 March - May 2013 Research Paper Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level Naveen Bolisetti*, Mothiram Bhukya** * Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. ** Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. Bolisetti, N., and Ram, M. B. (2013). Fuzzy Based Power Quality Improvement In Grid Connected Microgrid at the Distribution Level.  i-manager’s Journal on Circuits and Systems , 1(2), 1-6.  https://doi.org/10.26634/jcir.1.2.2288 Abstract This paper suggests a new control strategy that consists of a grid interfaced four leg inverter control system using adaptive fuzzy controller for a 3-phase 4-wire distribution system that is capable of simultaneously compensating problems like power factor, current imbalance and current harmonics, and also of inject...

Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs

Volume 5 Issue 4 September - November 2017 Research Paper Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs M. Chandra Sekhar Reddy*, P. Ramana Reddy** * Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapuramu, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India. Reddy, M. C. S., and Reddy, P. R. (2017). Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS.  i-manager’s Journal on Circuits and Systems , 5(4), 8-14.  https://doi.org/10.26634/jcir.5.4.13939 Abstract An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ...

Power Efficient Functional Units for High Speed Computations

Research Paper Power Efficient Functional Units for High Speed Computations B. Dinesh*, R. Jagadeesh**, M. Kathirvelu*** *,** PG Students, Department of ECE, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India. *** HOD & Professor, Department of Electronics and Communication, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu. Dinesh, B. Jagadeesh, R. and Kathirvelu, M. (2013). Power Efficient Functional Units For High Speed Computations.  i-manager’s Journal on Circuits and Systems , 1(3), 13-18.  https://doi.org/10.26634/jcir.1.3.2443 Abstract Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times ar...