i-manager's Journal on Circuits and Systems

Volume 5 Issue 2 March - May 2017 Research Paper Modeling of a PV Array and Implementation of an Efficient MPPT Based ControlMechanism in Stand-Alone Photovoltaic Systems Aarti Anil Ahlawat*, Diksha Gupta**, S. K. Gupta*** * PG Scholar, Deen Bandhu Chotu Ram University of Science and Technology, Sonepat, Haryana, India. ** Project Engineer, Wipro Technology, Greater Noida, India. *** Professor, Department of Electrical Engineering, DCR University of Science and Technology, Sonepat, Haryana, India.. Ahlawat, A., and Gupta, D. (2017). Modeling of a PV Array and Implementation of an Efficient MPPT Based Control Mechanism in Stand-Alone Photovoltaic Systems.  i-manager’s Journal on Circuits and Systems , 5(2), 51-61. https://doi.org/10.26634/jcir.5.2.13665 Abstract This paper provides a brief idea about modeling of Solar Photovoltaic systems. This paper presents simulation model of PV array which is used to evaluate the electrical performance of PV array with res...

Volume 5 Issue 2 March - May 2017 Research Paper Modelling, Simulation, and Harmonic Reduction of Five Level Diode ClampedInverter Fed Induction Motor Drive  Kuldeep Kumar**, V. K. Giri*** * Teaching-cum Research Scholar, Department of Electrical Engineering, IET, an autonomous institution of Dr. APJ Abdul Kalam Technical University, Lucknow, India. ** Professor, Department of Electrical Engineering, IET Lucknow, an autonomous institution of Dr. APJ Abdul Kalam Technical University, Lucknow, India. *** Professor, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India. Siddiqui, K. M., Sahay, K., Giri, V. K. (2017). Modelling, Simulation, and Harmonic Reduction of Five Level Diode Clamped Inverter Fed Induction Motor Drive.  i-manager’s Journal on Circuits and Systems , 5(2), 41-50. https://doi.org/10.26634/jcir.5.2.13664 Abstract In the present time, the multilevel inverters gained a large interest by the r...

Volume 5 Issue 2 March - May 2017 Research Paper Micro Hydro Power Familiarizing System Stand-In as a Smart Grid Pack ProposedFor Energy Depletion Ch. Venkateswara Rao*, S. S. Tulasi Ram**, B. Brahmaiah*** * Professor, Department of Electrical and Electronics Engineering, Gandhi Institute of Engineering and Technology, Gunupur, Odisha, India. ** Professor, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Hyderabad, India. *** Principal, Sri Vasavi Engineering College, Tadepalligudem, India. Rao, Ch. V., Tulasiram, S. S., Brahmaiah, B. (2017). Micro Hydro Power Familiarizing System Stand-In as a Smart Grid Pack Proposed For Energy Depletion.  i-manager’s Journal on Circuits and Systems , 5(2), 29-40. https://doi.org/10.26634/jcir.5.2.13663 Abstract The Hydroelectric power is generated by the rotating turbine through high pressure falling water that drives the generator. So far as electricity production is concer...

Volume 5 Issue 2 March - May 2017 Research Paper Energy Conservation by Energy Audit and Use of Energy Efficient Lamps Shekhappa G. Ankaliki*, Geetha M. M**, Divyabharati K.***, Bhagyashri P. M****, Jivita K.***** * Professor, Department of Electrical and Electronics Engineering, SDM College of Engineering & Technology, Dharwad, Karnataka, India. **-***** UG Scholar, Department of Electrical and Electronics Engineering, SDM College of Engineering & Technology, Karnataka, India. Ankaliki , S. G., Geetha, M. M., Divyabharati , K., Bhagyashri, P. M., Jivita, K. (2017). Energy Conservation by Energy Audit and Use Of Energy Efficient Lamps.  i-manager’s Journal on Circuits and Systems , 5(2), 20-28. https://doi.org/10.26634/jcir.5.2.13662 Abstract This paper presents energy conservation by energy audit and use of energy efficient lamps. In order to conserve energy and reduce electricity charges, energy audit is done for lighting system used in educational b...

Volume 5 Issue 2 March - May 2017 Research Paper Optimal Reference Power Tracking Of DFIG Converters Analysis at Low Wind Speedand Grid Disturbances Using Internal Model Controller D.V.N. Ananth* Assistant Professor, Department of Electrical Engineering, DADI Institute of Engineering and Technology, Anakapalli, India. Ananth, D. V. N. (2017). Optimal Reference Power Tracking Of DFIG Converters Analysis at Low Wind Speed and Grid Disturbances Using Internal Model Controller.  i-manager’s Journal on Circuits and Systems , 5(2), 1-19. https://doi.org/10.26634/jcir.5.2.13661 Abstract A pitch angle control based MPPT for turbine is modeled and a sensor-less rotor speed and torque estimation are proposed in this paper. Rotor Side Converter (RSC) proposed helps to achieve optimal real and reactive power from generator, which keeps rotor to rotate at optimal speed and quickly vary current flow from rotor and stator terminals. Grid Side Converter (GSC) proposed helps to ...

Volume 5 Issue 3 June - August 2017   Research Paper A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm Ishita Verma*, Priyanka Ghosh**, Upendra Soni***, Dharmendra Singh**** *-** UG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India. ***-**** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India. Verma, I., Ghosh , P., Soni, U., and Singh, D. (2017). A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm.  i-manager’s Journal on Circuits and Systems , 5(3), 38-42. https://doi.org/10.26634/jcir.5.3.13866 Abstract In this paper, a new architecture is proposed for multiplier and Accumulator ...

Volume 5 Issue 3 June - August 2017   Survey Paper Electromigration – A Brief Survey Satigouda Patil*, H. P. Rajani** * Research Scholar, VTU, Belgaum, India ** Professor, Department of Electronics and Communication Engineering, KLESCET, Belagavi, India. PATIL, S., and Rajani, H. P. (2017). Electromigration – A Brief Survey.  i-manager’s Journal on Circuits and Systems , 5(3), 31-37. https://doi.org/10.26634/jcir.5.3.13814 Abstract As the feature size shrinks, Electromigration (EM) becomes a more critical reliability issue in IC design. EM around the via structures account for much of the reliability problems in ICs [13]. Electromigration is increasingly relevant to physical design of the electronic circuits. It is caused by excess current density stress in the interconnect. The ongoing reduction of the circuit feature sizes has aggravated the problem over last couple of years. It is therefore an important reliability issue to consider electromigration-re...

Volume 5 Issue 3 June - August 2017   Review Paper Fault Location Estimation Systems: A Critical Review A. Sanad Ahmed*, Mahmoud A. Attia**, Nabil M. Hamed***,  * Deputy Project Manager, Siemens S.A.E, Egypt. **,*** Assistant Professor, Department of Electric Power and Machines, Ain Shams University, Egypt. **** Professor, Department of Electrical Power Engineering, Ain Shams University, Egypt. Sanad, A. A., Attia, M. A., Hamed, N. M., Abdelaziz, A. Y. (2017). Fault Location Estimation Systems: A Critical Review.  i-manager’s Journal on Circuits and Systems , 5(3), 17-30.  https://doi.org/10.26634/jcir.5.3.13813 Abstract Energy reliability is a critical aspect nowadays in energy management. Especially transmission system is considered a very essential part in the grid. Using transmission system all customers can get the energy needed for all applications on all voltage levels. So, if a fault occurs in the transmission system, this will lead to...

Volume 5 Issue 3 June - August 2017   Research Paper Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques M. Ranjit*, T. Brahmananda Reddy**, Surya Kalavathi M*** * Assistant Professor, Department of Electrical and Electronics Engineering, VNRVJIET, Bachupally, Hyderabad, Telangana, India. ** Head and Professor, Department of Electrical and Electronics Engineering, GPREC, Kurnool, Andhra Pradesh, India. *** Professor, Department of Electrical and Electronics Engineering, JNTUH, Kukatpally, Hyderabad, Telangana, India. Ranjit, M., Reddy, T. B., Suryakalavathi, M. (2017). Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques.  i-manager’s Journal on Circuits and Systems , 5(3), 10-16. https://doi.org/10.26634/jcir.5.3.13812 Abstract In this paper, decoupled space vector based PWM techniques are proposed for vector controlled open-end wind...

Volume 5 Issue 3 June - August 2017 Research Paper Performance Analysis of Adder Circuits Using FINFET'S Nancharaiah Vejendla*, R. Ramana Reddy**, N. Balaji*** * Research Scholar, Department of Electronics and Communication Engineering, JNTU Kakinada, India. ** Professor and Head, Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Viziangaram. India. *** Professor and Vice-principal, Department of Electronics and Communication Engineering (Admin), UCOE Narasaraopeta, JNTUK, India Vejendla, N., Reddy, P. R., Balaji, N. (2017). Performance Analysis of Adder Circuits Using FINFET'S.  i-manager’s Journal on Circuits and Systems , 5(3), 1-9.  https://doi.org/10.26634/jcir.5.3.13811 Abstract Due to scaling of conventional MOS transistors, leakage currents are increasing which leads to increase in power dissipation. Increase in power dissipation puts limit on scaling. To overcome the power dissipation problem, conventiona...

Volume 5 Issue 4 September - November 2017 Article Reaching Condition Techniques for Mitigation of Chattering In Sliding Mode Controlled Buck Converter K.B. Siddesh*, Basavaraja ** * Associate Professor, Department of Electronics and Communication Engineering, SJMIT, Chitradurga, India. ** Professor and Chairman, Department of Electrical and Electronics Engineering, UBDTCE, Davangere, India. Siddesh, K. B. and Banakara, B. (2017). Reaching Condition Techniques for Mitigation of Chattering in Sliding Mode Controlled Buck Converter.  i-manager’s Journal on Circuits and Systems , 5(4), 33-38.  https://doi.org/10.26634/jcir.5.4.13943 Abstract This paper presents a reaching condition methods for Sliding Mode Controlled DC-DC Buck Converter. Three approaches are specified for reaching conditions. The approaches comparing among the chattering, which is effectively reduced the chattering and fast speed is kept. The approaches are direct switching, lyapunov and re...

Volume 5 Issue 4 September - November 2017 Research Paper VLSI Design of Low Power High Speed Parallel Self Timed Adder for ALU Processing Circuits P. Lokesh*, U. Somalatha**, S. Chandana*** *-*** Assistant Professor, Vemu Institute of Technology, P. Kothakota, India. Lokesh, P., Somalatha, U., and Chandana, S. (2017). VLSI Design of Low Power High Speed Parallel Self Timed Adder for ALU Processing Circuits.  i-manager’s Journal on Circuits and Systems , 5(4), 27-32.  https://doi.org/10.26634/jcir.5.4.13942 Abstract Binary Addition is one of the most important arithmetic operation that a processor can execute. Such ALU process requires to be operated with high speed without degrading the performance of the circuit. Since VLSI mainly focus in area, delay and power consumption, a good VLSI circuit can maintain tradeoff between these parameters. In this paper, parallel Self Timed Adder is presented, which is capable of performing multipath binary addition. Thi...

Volume 5 Issue 4 September - November 2017 Research Paper Design of 63 Level Optimal Novel Cascaded Multilevel Inverter With Reduced Number of Switches and THD Bolla Madhusudan Reddy*, Y. V. Siva Reddy**, M. Vijaya Kumar*** * Research Scholar, Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India. ** Professor, Board of Studies Member, and Director of Research and Development, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India. *** Professor and Director of Admissions, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India. Reddy, B. M., Reddy, Y. V. S., Kumar, M. V. (2017). Design of 63 Level Optimal Novel Cascaded Multilevel Inverter With Reduced Number of Switches and THD.  i-manager’s Journal on Circuits and Systems , 5(4), 20-26. https://doi.org/10.26634/jcir.5.4.13941 Abstract This paper proposed a high level novel cascaded multilevel invert...

Volume 5 Issue 4 September - November 2017 Research Paper A Power Efficient NMOS Based Full Adder Using PTL Logic S. Iswariya*, M. Vilasini** * Assistant Professor, Department of Electronics and Communication Engineering, St.Peters Engineering College, Hyderabad, India. ** Associate Professor, Department of Electronics and Communication Engineering, St.Peters Engineering College, Hyderabad, India. Iswariya, S. and Raja, M. V. (2017). A Power Efficient NMOS Based Full Adder Using PTL Logic.  i-manager’s Journal on Circuits and Systems , 5(4), 15-19.  https://doi.org/10.26634/jcir.5.4.13940 Abstract Power dissipation is an important parameter in VLSI circuits. Previously it was ignored due to low device density and low operating frequency. Due to the challenging issues on high packing density, high operating frequency and increase in portable consumer electronics, high heat dissipation occurs which damages the performance. The previous method using 1 bit fu...

Volume 5 Issue 4 September - November 2017 Research Paper Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs M. Chandra Sekhar Reddy*, P. Ramana Reddy** * Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapuramu, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India. Reddy, M. C. S., and Reddy, P. R. (2017). Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS.  i-manager’s Journal on Circuits and Systems , 5(4), 8-14.  https://doi.org/10.26634/jcir.5.4.13939 Abstract An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ...

Volume 5 Issue 4 September - November 2017 Research Paper Continuous Overvoltage Characteristics of Surge Protected Power Strips Cengiz Polat* Assistant Professor, Department of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey. Uzunoglu, C. P. (2017). Continuous Over Voltage Characteristics of Surge Protected Power Strips.  i-manager’s Journal on Circuits and Systems,  5(4), 1-7.  https://doi.org/10.26634/jcir.5.4.13938 Abstract Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) ...

Volume 6 Issue 1 December - February 2018 Research Paper Performance Parameters of Low Power SRAM cells: A Review Nidhi Tiwari*, Vaibhav Neema**, Kamal J Rangra***, Yogesh Chandra Sharma**** * Research Scholar, Department of Electronics and Communication Engineering, Vivekananda Global University, Jaipur, India. ** Assistant Professor, Department of Electronics and Communication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, India. *** Chief Scientist, Transducers and Actuators Group, CSIR-CEERI, Pilani, India. **** Professor, Department of Physics, Vivekananda Global University, Jaipur, India. Tiwari, N., Neema, V., Rangra, K. J., and Sharma, Y. C. (2018). Performance Parameters of Low Power SRAM cells: A Review.  i-manager’s Journal on Circuits and Systems , 6(1), 25-34.  https://doi.org/10.26634/jcir.6.1.14495 Abstract In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis...