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A Power Efficient NMOS Based Full Adder Using PTL Logic


Volume 5 Issue 4 September - November 2017
Research Paper
A Power Efficient NMOS Based Full Adder Using PTL Logic
S. Iswariya*, M. Vilasini**
* Assistant Professor, Department of Electronics and Communication Engineering, St.Peters Engineering College, Hyderabad, India.
** Associate Professor, Department of Electronics and Communication Engineering, St.Peters Engineering College, Hyderabad, India.
Iswariya, S. and Raja, M. V. (2017). A Power Efficient NMOS Based Full Adder Using PTL Logic. i-manager’s Journal on Circuits and Systems, 5(4), 15-19. https://doi.org/10.26634/jcir.5.4.13940
Abstract
Power dissipation is an important parameter in VLSI circuits. Previously it was ignored due to low device density and low operating frequency. Due to the challenging issues on high packing density, high operating frequency and increase in portable consumer electronics, high heat dissipation occurs which damages the performance. The previous method using 1 bit full adder was not sufficient in handling high performance circuit. The proposed method reduces the power dissipation of a device and at the same time maintains an adequate throughput. For any processor, Full Adder is an important block for all processing and execution of mathematical models. By using Pass Transistor Logic (PTL) redundant transistors can be eliminated which in turn increases the speed and reduces the heat. The proposed method of including NMOS based PTL increases the performance of 1 bit and 8 bit full adder with more transistors in low area for an efficient power handling method. The results of the proposed work is compared with XOR existing method. The proposed full adder is efficient in terms of power, area.

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