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A Review on Approximation Techniques for Arithmetic Adders


Volume 6 Issue 2 March - May 2018
Review Paper
A Review on Approximation Techniques for Arithmetic Adders
S. M. Bhagat*
Department of Electronics and Telecommunication Engineering, Pimpri Chinchwad College of Engineering, Pune, India.
Bhagat, S. M. (2018). A Review on Approximation Techniques for Arithmetic Adders. i-manager’s Journal on Circuits and Systems, 6(2), 33-38. https://doi.org/10.26634/jcir.6.2.14313
Abstract
To design the computing system, energy efficiency is an important issue to be considered. Approximate computing has been evolved as an optimistic solution for energy efficient design of digital systems. While designing these systems, power dissipation is the significant issue for integrated circuits in nanometric Complementary Metal Oxide Semiconductor (CMOS) technology. Approximate implementations of a circuit have been considered as a potential solution for applications in which exact result is not required, which eventually reduces power consumption. The approximate computing has various research activities which varies from programming languages to transistor levels. Here, different approximate adder circuits have been reviewed, which are based on XOR and XNOR gates, and majority gates. Where emerging nanotechnology exploit these majority gates, combining with approximate computing gives the potential to reduce power consumption. Approximate circuit provides low power consumption, low transistor count, less area and reduced delay. Hence it is a good option, when strict exact solution is not required. This paper is about the survey on arithmetic circuits and different design topologies such as Quantum Dot Cellular Automata (QCA)and Nanomagnetic Logic (NML)

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