Volume 6 Issue 2 March - May 2018
Research Paper
G. Shivaprakash*, D. S. Suresh **
* Research Scholar and Associate
Professor, Department of Electronics and Instrumentation Engineering, Ramaiah
Institute of Technology, Bengaluru, Karnataka, India.
** Professor, Department of
Electronics and Communication Engineering, Chennabasaveshwara Institute of
Technology, Tumkure, Karnataka, India.
Shivaprakash, G., and Suresh, D. S.
(2018). Comparison of Power and Latency Optimized 7t SRAM Bit-Cell With 6t SRAM
Bit-Cell. i-manager’s Journal on Circuits and Systems, 6(2),
8-12. https://doi.org/10.26634/jcir.6.2.14760
Abstract
In today's smart
digital world, for any digital circuit, one of the most vital parts is Static
Random Access Memory (SRAM). The power consumption, speed, area etc. have been
the major areas of concern in the evolution of different memory architectures.
Researchers are working on the modification of basic 6T SRAM cell to meet their
requirements by optimizing the performance parameters of SRAM. In the present
research work, a novel 7T SRAM cell has been designed, having both low latency
and low power. The proposed design has allowed control over threshold voltage
and reduced the leakage current. As a consequence, there is a reduction in the
static power consumption and load capacitance of SRAM. Dynamic power
consumption, Static power consumption, Unit cell delay, Power Delay Product
(PDP), Static Noise Margin (SNM) and Write SNM are estimated for 6T and 7T for
comparison. On comparison of the performance parameters, the proposed 7T SRAM
cell was found to be the cell with least power consumption along with lowest
latency among the two cells. Most of the compared parameters show an improvement
in the performance of the proposed design as compared to the regular 6T
configuration of SRAM. This research was carried out using Cadence Virtuoso
Tools on 90 nm technology with Assura Verification tool and Spectre simulation
tool.
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