Skip to main content

Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology

Volume 6 Issue 3 June - August 2018
Research Paper
Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology
Sandhya Kesharwani*, Vaibhav Dedhe**
* PG Scholar, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.
** Assistant Professor, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.
Kesharwani, S., and Dedhe, V. (2018). Double Node Upset Radiation Immune Latch Design in 65nm CMOS Technology. i-manager’s Journal on Circuits and Systems, 6(3), 21-27. https://doi.org/10.26634/jcir.6.3.14624
Abstract
The space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles and heavy ions from solar flares. Nowadays most of the circuits used in space applications are being made of Complementary Metal Oxide Semiconductor (CMOS). The technology is scaling down, i.e. reduction in supply voltage and node capacitances lead to decrease of amount of charge stored on a node, which makes the circuit more vulnerable towards particle induced charge. When amount of this particle induced charge is high enough, a transient fault appears like a glitch called as Single Event Transient (SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double Node Upset (DNU) i.e Single Event Double Node Upset (SEDU). In this paper, some of the best known designs to mitigate the Single Event Upset as well as Single Event Double Node Upset in 65 nm CMOS technology using standard TSPICE tool has been discussed. The comparison of those designs on the same platform i.e 65 nm technology is presented, their power consumption and propagation delay are also compared.

Comments

Post a Comment

Popular posts from this blog

An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive

Volume 2 Issue 1 December - February 2014 Research Paper An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive Ayyappa Srinivasan M G*, Nirmal Singh** *Assistant Professor, Department of Electrical and Electronics Engineering, St.Mother Theresa Engineering College, Tuticorin, India. **Professor, Department of Electronics and Communication Engineering, V.V. College of Engineering, Tisayanvilai, India Srinivasan, A.M.G and Singh, N. N (2014). An Improved Multilevel Inverter With Lesser Number of Switches for an Induction Motor Drive.  i-manager’s Journal on Circuits and Systems , 2(1), 7-14.  https://doi.org/10.26634/jcir.2.1.2783 Abstract An improved three level inverter scheme, with less number of switches, having the features of common mode voltage elimination, DC link capacitor voltage balancing, and minimization and equalization of voltage stress across the switches, for an open end winding induction motor drive, h...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer

Volume 1 Issue 1 December - February 2013 Research Paper Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer S.Padmini*, Subransu Sekhar Dash**, S. Chandrasekhar***, Priyanka Vedula**** * Assistant Professor, SRM University. ** Professor and Head, Department of EEE, SRM University, Shruti. ***-**** B. Tech Student, SRM University. Padmini, S., Dash, S. S., Chandrasekhar, S. and Vedula, P. (2013). Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer.  i-manager’s Journal on Circuits and Systems , 1(1), 10-15.  https://doi.org/10.26634/jcir.1.1.2194 Abstract Advances Differential prot ecti on system is us e d t o protect most of the power transformers in power systems. The protection system is based on the differential currents/voltages of the primary an d secondary of the transformers under fault conditions and under normal operating conditions. The inrus currents or the magnetizing currents are generated in the...
Post a Comment
Read more