Skip to main content

High Speed and Low Power 4*4 Array Multiplier Design


Volume 7 Issue 1 December - February 2019
Research Paper
High Speed and Low Power 4*4 Array Multiplier Design
N. Suresh*, K. S. Shaji**, M. Chaitanya Kishore Reddy***
*_** Professor, Department of Electronics and Communication Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.
*** Professor, Department of Computer Science Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.
Suresh,N., Shaji, K. S., and Reddy, M. C. K. (2019). High Speed and Low Power 4*4 Array Multiplier Design. i-manager's Journal on Circuits and Systems , 7(1), 24-29. https://doi.org/10.26634/jcir.7.1.15530
Abstract
The main objective of this research is to design a Low power 4*4 Array Multiplier using modified GDI based full adder techniques, which consumes low power and have high speed computation compared to the CMOS technology. The modification has implemented in full adder design using GDI techniques in which the logical circuit reduces the number of transistors in the overall schematic. As we design any types of multiplier, the main logical block is adder and AND gate, similarly in this research also the authors concentrate to design Low power 4*4 Multiplier, which contains 8 full adder blocks. In these blocks, a modified GDI based full adder technology has been introduced. This way of reducing the number of transistors reduces the power consumption of overall circuits, propagation delay, and surface area. At the same time, the computation speed of the multipliers is increased.

Comments

Post a Comment

Popular posts from this blog

Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level

Volume 1 Issue 2 March - May 2013 Research Paper Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level Naveen Bolisetti*, Mothiram Bhukya** * Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. ** Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. Bolisetti, N., and Ram, M. B. (2013). Fuzzy Based Power Quality Improvement In Grid Connected Microgrid at the Distribution Level.  i-manager’s Journal on Circuits and Systems , 1(2), 1-6.  https://doi.org/10.26634/jcir.1.2.2288 Abstract This paper suggests a new control strategy that consists of a grid interfaced four leg inverter control system using adaptive fuzzy controller for a 3-phase 4-wire distribution system that is capable of simultaneously compensating problems like power factor, current imbalance and current harmonics, and also of inject...
Post a Comment
Read more

Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs

Volume 5 Issue 4 September - November 2017 Research Paper Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs M. Chandra Sekhar Reddy*, P. Ramana Reddy** * Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapuramu, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India. Reddy, M. C. S., and Reddy, P. R. (2017). Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS.  i-manager’s Journal on Circuits and Systems , 5(4), 8-14.  https://doi.org/10.26634/jcir.5.4.13939 Abstract An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ...
Post a Comment
Read more

Power Efficient Functional Units for High Speed Computations

Research Paper Power Efficient Functional Units for High Speed Computations B. Dinesh*, R. Jagadeesh**, M. Kathirvelu*** *,** PG Students, Department of ECE, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India. *** HOD & Professor, Department of Electronics and Communication, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu. Dinesh, B. Jagadeesh, R. and Kathirvelu, M. (2013). Power Efficient Functional Units For High Speed Computations.  i-manager’s Journal on Circuits and Systems , 1(3), 13-18.  https://doi.org/10.26634/jcir.1.3.2443 Abstract Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times ar...
Post a Comment
Read more