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High Speed and Low Power 4*4 Array Multiplier Design


Volume 7 Issue 1 December - February 2019
Research Paper
High Speed and Low Power 4*4 Array Multiplier Design
N. Suresh*, K. S. Shaji**, M. Chaitanya Kishore Reddy***
*_** Professor, Department of Electronics and Communication Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.
*** Professor, Department of Computer Science Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.
Suresh,N., Shaji, K. S., and Reddy, M. C. K. (2019). High Speed and Low Power 4*4 Array Multiplier Design. i-manager's Journal on Circuits and Systems , 7(1), 24-29. https://doi.org/10.26634/jcir.7.1.15530
Abstract
The main objective of this research is to design a Low power 4*4 Array Multiplier using modified GDI based full adder techniques, which consumes low power and have high speed computation compared to the CMOS technology. The modification has implemented in full adder design using GDI techniques in which the logical circuit reduces the number of transistors in the overall schematic. As we design any types of multiplier, the main logical block is adder and AND gate, similarly in this research also the authors concentrate to design Low power 4*4 Multiplier, which contains 8 full adder blocks. In these blocks, a modified GDI based full adder technology has been introduced. This way of reducing the number of transistors reduces the power consumption of overall circuits, propagation delay, and surface area. At the same time, the computation speed of the multipliers is increased.

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