Skip to main content

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency


Volume 6 Issue 3 June - August 2018
Research Paper
Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency
Tripti Nirmalkar*, Deepti Kanoujia**, Kshitiz Varma***
* PG Scholar, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University,Chhattisgarh, India.
** Post Graduate, Department of Electronics and Communication Engineering, Sri Shankaracharya College of Engineering and Technology, Chhattisgarh, India.
*** Project Officer, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University, Chhattisgarh, India.
Nirmalkar, T., Kanoujia, D., and Varma, K. (2018). Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency. i-manager’s Journal on Circuits and Systems, 6(3), 36-42.https://doi.org/10.26634/jcir.6.3.14877
Abstract
Research on reversible logic gates has become one of the interesting fields in the world of electronics. This has been proved to be one of the most reliable logics that originates its place in low power CMOS skills, Nano and optical calculation and many more. These broadsheet offers the comparison of different reversible logic gates in expressions of quantum cost, delay, transistor charge, and also implementation of one of the alterable logic gates, i.e. Peres gate in a conventional half adder with the help of an efficient algorithm. The work is performed in Xilinx using Verilog coding. The simulation result shows improved efficiency, low power, and low area consumption as related to the standard half adder. This half adder can be utilized in different applications, where circuit comprising of a conventional half adder can be replaced by Peres Half Adder (HAP).

Comments

Post a Comment

Popular posts from this blog

Continuous Overvoltage Characteristics of Surge Protected Power Strips

Volume 5 Issue 4 September - November 2017 Research Paper Continuous Overvoltage Characteristics of Surge Protected Power Strips Cengiz Polat* Assistant Professor, Department of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey. Uzunoglu, C. P. (2017). Continuous Over Voltage Characteristics of Surge Protected Power Strips.  i-manager’s Journal on Circuits and Systems,  5(4), 1-7.  https://doi.org/10.26634/jcir.5.4.13938 Abstract Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) ...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

A Review on Control strategies for LFC in Deregulated Scenario

Volume 1 Issue 1 December - February 2013 Review Paper A Review on Control strategies for LFC in Deregulated Scenario T. Anilkumar*, N. Venkata ramana** * Associate Professor, EEE Department, ACE Engineering College, Ghatkesar, Hyderabad, AP, India. ** Professor and Head of Deportment, EEE Department, JNTU Mantini, AP, India. Kumar, T. A., and Ramana, N., (2013). A Review On Control Strategies For LFC In Deregulated Scenario.  i-manager’s Journal on Circuits and Systems , 1(1), 27-36.  https://doi.org/10.26634/jcir.1.1.2197 Abstract In power system studies, Load frequency control is an important issue to supply sufficient and reliable electric power with good quality. The main objective of LFC is to maintain load frequency and tie-line power flow within permissible limits by adjusting megawatt output of LFC generators, so as to accommodate fluctuating load demands. This paper presents a brief review of different control techniques to researchers on design...
Post a Comment
Read more