Skip to main content

Novel Setup Time Model for Standard Cell Library Characterization


Volume 6 Issue 3 June - August 2018
Research Paper
Novel Setup Time Model for Standard Cell Library Characterization
Pravee Jain*, Sharad Mohan Shrivastava**
* PG Scholar, Department of Electronics and Communication Engineering, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.
** Assistant Professor, Department of Electronics and Communication, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.
Jain, P., and Shrivastava, S., M. (2018). Novel Setup Time Model for Standard Cell Library Characterization. i-manager’s Journal on Circuits and Systems, 6(3), 9-14. https://doi.org/10.26634/jcir.6.3.14566
Abstract
In digital VLSI design calculation of setup/hold time is very important part. Setup/hold time defines the maximum speed of the circuit on which it can work. When a design is completed the first step is to check the timing performances of circuit using Static Timing Analysis (STA) (Scheffer et al., 2006). Accuracy of STA depends on the data described in standard cell libraries. So accuracy of STA depends on accuracy of standard cell library characterization (Cirit, 1991; Roethig, 2003; Patel, 1990; Phelps, 1991). As the technology is scaling down, the characterization of standard cell libraries are becoming more time consuming and requires large computational time. Further due to process, voltage and temperature (PVT) variations standard cell library characterization is done for various PVT, this increase characterization greatly. In this paper we present a novel approach to speed up standard cell library characterization for true single phase clocked (TSPC) latch (Yuan and Svensson, 1989) setup time by developing a linear setup time model. In this model setup time varies linearly with output load capacitance (CL) and input transition time (TR). We express setup time model coefficients as a function of logic gate size (Wn) of the latch. We do not use device current/capacitance models in derivation of model, so it is valid with technology scaling. Using proposed model approximately 70% SPICE simulation during the standard cell library characterization for latch setup time can be saved. We observed that setup time calculated using proposed model is within 2% (average) of that calculated using simulation.

Comments

Post a Comment

Popular posts from this blog

Continuous Overvoltage Characteristics of Surge Protected Power Strips

Volume 5 Issue 4 September - November 2017 Research Paper Continuous Overvoltage Characteristics of Surge Protected Power Strips Cengiz Polat* Assistant Professor, Department of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey. Uzunoglu, C. P. (2017). Continuous Over Voltage Characteristics of Surge Protected Power Strips.  i-manager’s Journal on Circuits and Systems,  5(4), 1-7.  https://doi.org/10.26634/jcir.5.4.13938 Abstract Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) ...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

A Review on Control strategies for LFC in Deregulated Scenario

Volume 1 Issue 1 December - February 2013 Review Paper A Review on Control strategies for LFC in Deregulated Scenario T. Anilkumar*, N. Venkata ramana** * Associate Professor, EEE Department, ACE Engineering College, Ghatkesar, Hyderabad, AP, India. ** Professor and Head of Deportment, EEE Department, JNTU Mantini, AP, India. Kumar, T. A., and Ramana, N., (2013). A Review On Control Strategies For LFC In Deregulated Scenario.  i-manager’s Journal on Circuits and Systems , 1(1), 27-36.  https://doi.org/10.26634/jcir.1.1.2197 Abstract In power system studies, Load frequency control is an important issue to supply sufficient and reliable electric power with good quality. The main objective of LFC is to maintain load frequency and tie-line power flow within permissible limits by adjusting megawatt output of LFC generators, so as to accommodate fluctuating load demands. This paper presents a brief review of different control techniques to researchers on design...
Post a Comment
Read more