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Performance Parameters of Low Power SRAM cells: A Review


Volume 6 Issue 1 December - February 2018
Research Paper
Performance Parameters of Low Power SRAM cells: A Review
Nidhi Tiwari*, Vaibhav Neema**, Kamal J Rangra***, Yogesh Chandra Sharma****
* Research Scholar, Department of Electronics and Communication Engineering, Vivekananda Global University, Jaipur, India.
** Assistant Professor, Department of Electronics and Communication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, India.
*** Chief Scientist, Transducers and Actuators Group, CSIR-CEERI, Pilani, India.
**** Professor, Department of Physics, Vivekananda Global University, Jaipur, India.
Tiwari, N., Neema, V., Rangra, K. J., and Sharma, Y. C. (2018). Performance Parameters of Low Power SRAM cells: A Review. i-manager’s Journal on Circuits and Systems, 6(1), 25-34. https://doi.org/10.26634/jcir.6.1.14495
Abstract
In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis of power, stability, and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell are high in speed but at low supply voltage, stability is a critical issue. It is found that 8T SRAM cell shows the highest level of stability at low supply voltage, but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example, machine learning needs high performance memory block while bio-medical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.

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