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Validation of IOV chain using OVM Technique


Volume 6 Issue 3 June - August 2018
Research Paper
Validation of IOV chain using OVM Technique
S. Gayathri*, S. Lavanya **
* Professor, Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India.
** Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India.
Gayathri, S., and Lavanya, S. (2018). Validation of IOV Chain using OVM Technique. i-manager’s Journal on Circuits and Systems, 6(3), 28-35. https://doi.org/10.26634/jcir.6.3.14632
Abstract
Today, the utilization of pre-silicon system verification strategies within the business cannot guarantee that every error in system computer code or system hardware are discovered and removed before silicon (Si) becomes offered. Some system errors solely show up once the application software package is executed on the particular Si. Presently, the business spends on average more than 50% of the overall project time on post-silicon validation and debugging. At this stage, it is still terribly tough and time intense to rectify issues that ends up in higher development price, slippery deadlines, and a possible loss of consumer. Therefore, an efficient method for debugging errors is used called Design for Debug (DFD). The DFD strategies prevailing nowadays are everywhere for over a decade. There are numerous examples throughout the industry, where the inclusion and subsequent use of DFD features have contributed significantly to a reduction in Time to Market (TTM). This paper proposes a DFD Validation of In-die variation (IDV), On-die Droop inducer (ODI), and Voltage Droop monitor (VDM) to reduce manufacturing defects or errors of chip, such as Variation of Process, Power Domain voltages and also variation of current inducer needed for chip.

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