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VLSI Design of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation


Volume 6 Issue 1 December - February 2018
Research Paper
VLSI Design of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation
P. Lokesh*, S.Chandana **, U.Somalatha ***
*-*** Assistant Professor, Department of Electronics and Communication Engineering, VEMU Institute of Technology, P. Kothakota, India.
Lokesh, P., Chandana, S., and Somalatha, U. (2018). VLSI Design Of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation. i-manager’s Journal on Circuits and Systems, 6(1), 8-13.https://doi.org/10.26634/jcir.6.1.14494
Abstract
n this paper, an efficient Distributed Arithmetic (DA) based reconfigurable Finite Impulse Response (FIR) digital filter is presented which is designed to yield high performance and throughput. To achieve this, the FIR filter co-efficients are designed to change automatically during the processing time. The primary hardware component in the DA based FIR filter is Look-up-Tables (LUTs). In existing architecture to design a filter, RAM based LUTs are used which is not practical for implementing the design as the arithmetic processing partial products are stored in the RAM that thereby consumes more memory blocks. Other limitation of RAM based DA is the structure. It is more cost effective to implement the design in ASIC. To overcome this limitation, shared LUTs are proposed, where instead of storing all the partial inner products in the RAM, shared registers are used to store the bit positions based on the weightage, thereby reducing the use of hardware components when compared with the CSA based structure. The proposed design has less Area-Delay product and less energy per sample. Simulation and synthesis results are verified by using Xilinx 14.2 synthesis tool and Virtex-5 FPGA is the target device. The experimental results show that the proposed design is more efficient than the previous works.

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