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VLSI Design of Low Power High Speed Parallel Self Timed Adder for ALU Processing Circuits


Volume 5 Issue 4 September - November 2017
Research Paper
VLSI Design of Low Power High Speed Parallel Self Timed Adder for ALU Processing Circuits
P. Lokesh*, U. Somalatha**, S. Chandana***
*-*** Assistant Professor, Vemu Institute of Technology, P. Kothakota, India.
Lokesh, P., Somalatha, U., and Chandana, S. (2017). VLSI Design of Low Power High Speed Parallel Self Timed Adder for ALU Processing Circuits. i-manager’s Journal on Circuits and Systems, 5(4), 27-32. https://doi.org/10.26634/jcir.5.4.13942
Abstract
Binary Addition is one of the most important arithmetic operation that a processor can execute. Such ALU process requires to be operated with high speed without degrading the performance of the circuit. Since VLSI mainly focus in area, delay and power consumption, a good VLSI circuit can maintain tradeoff between these parameters. In this paper, parallel Self Timed Adder is presented, which is capable of performing multipath binary addition. This parallel operation do not generate carry chain propagations thereby speedup the circuitry. One advantage of parallel adder is it maintains the tradeoff between Fan-in and Fan-out by incorporating suitable transistors in parallel. The design is implemented in Xilinx ISE14.2 synthesis tool with Virtex-5 FPGA as the target hardware equipment. For backend analysis, the XOR gate and multiplexers are designed by using extended Dual Mode Logic Technique and layouts are designed in Microwind3.1 at 32 nm CMOS Technology The simulation and synthesis results reveals the fact the parallel self timed adder have the potential to run faster when compared with existing asynchronous adder.

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