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Design and Verification of 16-Bit RISC Processor using SystemVerilog


Volume 6 Issue 4 September - November 2018
Research Paper
Design and Verification of 16-Bit RISC Processor using SystemVerilog
S. M. Bhagat*, S. U. Bhandari**
* PG Scholar, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.
** Professor, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.
Bhagat, S. M., Bhandari, S. U. (2018). Design and Verification of 16-Bit RISC Processor using System Verilog, i-manager's Journal on Circuits and Systems, 6(4), 38-41. https://doi.org/10.26634/jcir.6.4.14864
Abstract
The regularly increasing complexity and size of the designs faces various issues with traditional verification methods. To address this issue a reuse-oriented, verification methodology should be adopted which is built on the rich semantic support of a standard language. This paper presents a design of a 16 bit RISC processor with 15 instructions. The design is described in each module and the performance of the design is also presented in convenient manner. Although the design cycle takes time, but more time is required for verification. To perform verification process, verification environment is built for few modules of this RISC processor using SystemVerilog. Among various verification methodologies here a simple approach of verification is presented.

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