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A High Speed Floating Point Multiplier using Vedic Mathematics

Volume 2 Issue 2 March - May 2014
Research Paper
A High Speed Floating Point Multiplier using Vedic Mathematics
Duvvuru Praveen Kumar*, M. Bharathi**
* M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupathi.
** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupathi
Kumar, D. P., and Bharathi, M. (2014). A High Speed Floating Point Multiplier using Vedic Mathematics. i-manager’s Journal on Circuits and Systems, 2(2), 1-9. https://doi.org/10.26634/jcir.2.2.2973
Abstract
In this paper, the authors present an efficient implementation of Floating point multiplier which decreases delay of the circuit and this is done by replacing the multiplier block in the floating point multiplier and by comparing the delays in multiplication for each and every multiplier. In this paper, they use a standard floating point format i.e., IEEE 754 (which is a common standard for both Single Precision and Double Precision Floating point multipliers). Floating Point multiplication is an important factor in most DSP Applications. The other requirement of DSP applications in their fabrication is less area and low power consumption and less delay, also the performance matters in DSP systems. DSP systems require high performance. In this paper, the authors relate all the requirements of the DSP applications with respect to its speed. They have compared various multipliers as said before and have produced the best multiplier for floating point multiplication in terms of speed. This paper can be implemented using verilog HDL or VHDL and is checked in XILINX ISE 10.1 of FPGA.

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