Skip to main content

A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm


Volume 2 Issue 4 September - November 2014
Research Paper
A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm
R. Mohanapriya*, K. Rajesh**, P. S. Sudarshana***
* PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, India.
** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
*** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
Mohanapriya, R., Rajesh, K., and Sudarshana, P. S. (2014). Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 2(4), 1-6. https://doi.org/10.26634/jcir.2.4.3218
Abstract
The Multiplier-and-Accumulator (MAC) unit is the basic element of the digital signal processing(DSP) applications such as filtering, convolution, transformations and Inner products. So the MAC should provide high speed multiplication and multiplication with accumulative addition. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products. The objective of the paper is to reduce the power consumption using Modified Booth Algorithm and Spurious Power Suppression Technique. And also to increase the speed of operation by decreasing the number of MAC stages. By using radix-4 Modified Booth Algorithm, partial products are reduced by half and then by using Spurious Power Suppression Technique power has been reduced. In this architecture, multiplication and accumulation have been combined with a hybrid type of Carry Save Adder (CSA). In booth multiplication, when two numbers are multiplied, some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose, Spurious Power Suppression Technique (SPST) is used to remove ineffective portion of the data in addition process. The modified MAC operation is coded with Verilog and simulated using Xilinx ISE 12.1.

Comments

Post a Comment

Popular posts from this blog

Continuous Overvoltage Characteristics of Surge Protected Power Strips

Volume 5 Issue 4 September - November 2017 Research Paper Continuous Overvoltage Characteristics of Surge Protected Power Strips Cengiz Polat* Assistant Professor, Department of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey. Uzunoglu, C. P. (2017). Continuous Over Voltage Characteristics of Surge Protected Power Strips.  i-manager’s Journal on Circuits and Systems,  5(4), 1-7.  https://doi.org/10.26634/jcir.5.4.13938 Abstract Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) ...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

A Review on Control strategies for LFC in Deregulated Scenario

Volume 1 Issue 1 December - February 2013 Review Paper A Review on Control strategies for LFC in Deregulated Scenario T. Anilkumar*, N. Venkata ramana** * Associate Professor, EEE Department, ACE Engineering College, Ghatkesar, Hyderabad, AP, India. ** Professor and Head of Deportment, EEE Department, JNTU Mantini, AP, India. Kumar, T. A., and Ramana, N., (2013). A Review On Control Strategies For LFC In Deregulated Scenario.  i-manager’s Journal on Circuits and Systems , 1(1), 27-36.  https://doi.org/10.26634/jcir.1.1.2197 Abstract In power system studies, Load frequency control is an important issue to supply sufficient and reliable electric power with good quality. The main objective of LFC is to maintain load frequency and tie-line power flow within permissible limits by adjusting megawatt output of LFC generators, so as to accommodate fluctuating load demands. This paper presents a brief review of different control techniques to researchers on design...
Post a Comment
Read more