Skip to main content

A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm


Volume 2 Issue 4 September - November 2014
Research Paper
A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm
R. Mohanapriya*, K. Rajesh**, P. S. Sudarshana***
* PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, India.
** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
*** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
Mohanapriya, R., Rajesh, K., and Sudarshana, P. S. (2014). Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 2(4), 1-6. https://doi.org/10.26634/jcir.2.4.3218
Abstract
The Multiplier-and-Accumulator (MAC) unit is the basic element of the digital signal processing(DSP) applications such as filtering, convolution, transformations and Inner products. So the MAC should provide high speed multiplication and multiplication with accumulative addition. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products. The objective of the paper is to reduce the power consumption using Modified Booth Algorithm and Spurious Power Suppression Technique. And also to increase the speed of operation by decreasing the number of MAC stages. By using radix-4 Modified Booth Algorithm, partial products are reduced by half and then by using Spurious Power Suppression Technique power has been reduced. In this architecture, multiplication and accumulation have been combined with a hybrid type of Carry Save Adder (CSA). In booth multiplication, when two numbers are multiplied, some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose, Spurious Power Suppression Technique (SPST) is used to remove ineffective portion of the data in addition process. The modified MAC operation is coded with Verilog and simulated using Xilinx ISE 12.1.

Comments

Post a Comment

Popular posts from this blog

Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level

Volume 1 Issue 2 March - May 2013 Research Paper Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level Naveen Bolisetti*, Mothiram Bhukya** * Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. ** Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. Bolisetti, N., and Ram, M. B. (2013). Fuzzy Based Power Quality Improvement In Grid Connected Microgrid at the Distribution Level.  i-manager’s Journal on Circuits and Systems , 1(2), 1-6.  https://doi.org/10.26634/jcir.1.2.2288 Abstract This paper suggests a new control strategy that consists of a grid interfaced four leg inverter control system using adaptive fuzzy controller for a 3-phase 4-wire distribution system that is capable of simultaneously compensating problems like power factor, current imbalance and current harmonics, and also of inject...
Post a Comment
Read more

Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs

Volume 5 Issue 4 September - November 2017 Research Paper Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs M. Chandra Sekhar Reddy*, P. Ramana Reddy** * Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapuramu, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India. Reddy, M. C. S., and Reddy, P. R. (2017). Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS.  i-manager’s Journal on Circuits and Systems , 5(4), 8-14.  https://doi.org/10.26634/jcir.5.4.13939 Abstract An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ...
Post a Comment
Read more

Power Efficient Functional Units for High Speed Computations

Research Paper Power Efficient Functional Units for High Speed Computations B. Dinesh*, R. Jagadeesh**, M. Kathirvelu*** *,** PG Students, Department of ECE, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India. *** HOD & Professor, Department of Electronics and Communication, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu. Dinesh, B. Jagadeesh, R. and Kathirvelu, M. (2013). Power Efficient Functional Units For High Speed Computations.  i-manager’s Journal on Circuits and Systems , 1(3), 13-18.  https://doi.org/10.26634/jcir.1.3.2443 Abstract Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times ar...
Post a Comment
Read more