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A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm


Volume 2 Issue 4 September - November 2014
Research Paper
A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm
R. Mohanapriya*, K. Rajesh**, P. S. Sudarshana***
* PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, India.
** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
*** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.
Mohanapriya, R., Rajesh, K., and Sudarshana, P. S. (2014). Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 2(4), 1-6. https://doi.org/10.26634/jcir.2.4.3218
Abstract
The Multiplier-and-Accumulator (MAC) unit is the basic element of the digital signal processing(DSP) applications such as filtering, convolution, transformations and Inner products. So the MAC should provide high speed multiplication and multiplication with accumulative addition. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products. The objective of the paper is to reduce the power consumption using Modified Booth Algorithm and Spurious Power Suppression Technique. And also to increase the speed of operation by decreasing the number of MAC stages. By using radix-4 Modified Booth Algorithm, partial products are reduced by half and then by using Spurious Power Suppression Technique power has been reduced. In this architecture, multiplication and accumulation have been combined with a hybrid type of Carry Save Adder (CSA). In booth multiplication, when two numbers are multiplied, some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose, Spurious Power Suppression Technique (SPST) is used to remove ineffective portion of the data in addition process. The modified MAC operation is coded with Verilog and simulated using Xilinx ISE 12.1.

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