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An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Volume 4 Issue 3 June - August 2016

Research Paper

An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Naman Saxena*, Neeta Pandey**
*-** UG Scholar, Department of Electrical and Electronics Engineering, Delhi Technological University, India.
*** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, India.
Saxena, N., Dutta, S., and Pandey, N. (2016). An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline. i-manager’s Journal on Circuits and Systems, 4(3), 6-14. https://doi.org/10.26634/jcir.4.3.8219

Abstract


In this paper, Positive Feedback Source Coupled Logic (PFSCL) based asynchronous pipeline implementation is addressed. Existing Conventional PFSCL and a more efficient Triple-Tail Cell-based PFSCL variant are used for this purpose. Striking a trade-off between both topologies, a new hybrid implementation of the pipeline has been proposed. The concept is elucidated through FIFO sequencer. The hybrid implementation of asynchronous pipeline results in lesser number of gates as well as lower average power dissipation, thus not only making the circuit more efficient but also reducing overall area overhead. The validity of the proposal is confirmed through SPICE simulations using 0.18 um CMOS technology parameters.

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