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An Efficient Low Power Multiplier Using SubthresholdAdiabatic Logic


Volume 2 Issue 3 June - August 2014
Research Paper
An Efficient Low Power Multiplier Using SubthresholdAdiabatic Logic
Tounga Mounika*, Duvvuru Praveen Kumar**, M. Bharathi***
*,** M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.
*** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.
Mounika, T., Kumar, D. P., and Bharathi, M. (2014). An Efficient Low Power Multiplier Using Subthreshold Adiabatic Logic. i-manager’s Journal on Circuits and Systems, 2(3), 7-11. https://doi.org/10.26634/jcir.2.3.3161
Abstract
Multiplication Algorithms have considerable effect on processors’ performance. Multiplier is an important circuit used in electronic industry especially in Digital Signal Processing operations such as filtering, convolution and analysis of frequency. There are different types of algorithms used in multipliers to achieve the better performance. In this paper, 8*8 Wallace Tree and Dadda multipliers are implemented using two phase clocking subthreshold adiabatic logic. Its power dissipation is less when compared to their respective 8*8 CMOS multipliers. This paper can be implemented in HSPICE using 0.18μm CMOS standard process technology

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