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An Energy Efficient Tri State Buffer Logic Using Subthreshold Adiabatic


Volume 3 Issue 1 December - February 2015
Research Paper
An Energy Efficient Tri State Buffer Logic Using Subthreshold Adiabatic
M. Bharathi*
Assistant Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupathi.
Bharathi, M. (2015). An Energy Efficient Tri State Buffer Logic Using Subthreshold Adiabatic. i-manager’s Journal on Circuits and Systems, 3(1), 1-4. https://doi.org/10.26634/jcir.3.1.3256
Abstract
Tristate buffer is used in many applications such as electronics, communications and microprocessor circuits where they allow many devices to be connected to the same wire or bus without damage or loss of information. Contention occurs, if multiple devices are connected to same data bus. In general, digital information can be sent either serially or in parallel. For example, in microprocessor, information can be sent through data high way buses which allow multiple Tristate buffers to be connected together without loss of information. In general, buffer not only provides isolation, but also used to provide current or voltage amplification to drive heavy loads. These Tristate buffer devices can be used as bidirectional switches, because they are constructed using MOSFETS. This paper provides an energy efficient tristate buffer which is implemented using static CMOS, adiabatic and two Subthreshold adiabatic in HSPICE using 0.18μm CMOS standard process technology. The results obtained in the paper is effective in terms of power and area.

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