Volume 3 Issue 3 June - August 2015
Research Paper
Neeta Pandey*, Nalin Dadhich**, Mohd.
Zubair Talha***
* Associate Professor, Department of
Electronics and Communication Engineering, Delhi Technological University,
India.
**_*** UG Scholar, Department of
Electronics and Communication Engineering, Delhi Technological University,
India.
Pandey, N., Dadhich, N., and Talha,
M. Z. (2015). An Optimized and Cost Efficient Realization of Reversible Braun
Multiplier. i-manager’s Journal on Circuits and Systems, 3(3),
17-24. https://doi.org/10.26634/jcir.3.3.4781
Abstract
In CMOS logic, there is a
steady increase in power dissipation which appears in the form of heat to the
surrounding environment and affects the reliability. The research efforts are
made towards looking into alternatives that go beyond the traditional CMOS
technologies, and reversible logic has emerged as a promising choice. In this
paper, an optimized and cost efficient realization of reversible Braun
multiplier is presented. The design of a 4x4 bit multiplier is developed, designed
and presented in this paper as an illustration. The architecture is iterative
and hence this can easily be extended to the generalized multiplier of any
order. The proposed design of a 4x4 reversible Braun multiplier uses three
types of reversible gates namely, PG, HNG and TG gates. The proposed design is
compared with an already presented reversible multiplier design showing that
the proposed multiplier design is more efficient in terms of quantum cost,
constant inputs, garbage outputs and the number of elementary reversible gates.
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