Skip to main content

An Optimized and Cost Efficient Realization of Reversible Braun Multiplier

Volume 3 Issue 3 June - August 2015
Research Paper
An Optimized and Cost Efficient Realization of Reversible Braun Multiplier
Neeta Pandey*, Nalin Dadhich**, Mohd. Zubair Talha***
* Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, India.
**_*** UG Scholar, Department of Electronics and Communication Engineering, Delhi Technological University, India.
Pandey, N., Dadhich, N., and Talha, M. Z. (2015). An Optimized and Cost Efficient Realization of Reversible Braun Multiplier. i-manager’s Journal on Circuits and Systems, 3(3), 17-24. https://doi.org/10.26634/jcir.3.3.4781
Abstract
In CMOS logic, there is a steady increase in power dissipation which appears in the form of heat to the surrounding environment and affects the reliability. The research efforts are made towards looking into alternatives that go beyond the traditional CMOS technologies, and reversible logic has emerged as a promising choice. In this paper, an optimized and cost efficient realization of reversible Braun multiplier is presented. The design of a 4x4 bit multiplier is developed, designed and presented in this paper as an illustration. The architecture is iterative and hence this can easily be extended to the generalized multiplier of any order. The proposed design of a 4x4 reversible Braun multiplier uses three types of reversible gates namely, PG, HNG and TG gates. The proposed design is compared with an already presented reversible multiplier design showing that the proposed multiplier design is more efficient in terms of quantum cost, constant inputs, garbage outputs and the number of elementary reversible gates.

Comments

Post a Comment

Popular posts from this blog

An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive

Volume 2 Issue 1 December - February 2014 Research Paper An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive Ayyappa Srinivasan M G*, Nirmal Singh** *Assistant Professor, Department of Electrical and Electronics Engineering, St.Mother Theresa Engineering College, Tuticorin, India. **Professor, Department of Electronics and Communication Engineering, V.V. College of Engineering, Tisayanvilai, India Srinivasan, A.M.G and Singh, N. N (2014). An Improved Multilevel Inverter With Lesser Number of Switches for an Induction Motor Drive.  i-manager’s Journal on Circuits and Systems , 2(1), 7-14.  https://doi.org/10.26634/jcir.2.1.2783 Abstract An improved three level inverter scheme, with less number of switches, having the features of common mode voltage elimination, DC link capacitor voltage balancing, and minimization and equalization of voltage stress across the switches, for an open end winding induction motor drive, h...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer

Volume 1 Issue 1 December - February 2013 Research Paper Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer S.Padmini*, Subransu Sekhar Dash**, S. Chandrasekhar***, Priyanka Vedula**** * Assistant Professor, SRM University. ** Professor and Head, Department of EEE, SRM University, Shruti. ***-**** B. Tech Student, SRM University. Padmini, S., Dash, S. S., Chandrasekhar, S. and Vedula, P. (2013). Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer.  i-manager’s Journal on Circuits and Systems , 1(1), 10-15.  https://doi.org/10.26634/jcir.1.1.2194 Abstract Advances Differential prot ecti on system is us e d t o protect most of the power transformers in power systems. The protection system is based on the differential currents/voltages of the primary an d secondary of the transformers under fault conditions and under normal operating conditions. The inrus currents or the magnetizing currents are generated in the...
Post a Comment
Read more