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An Optimized Low Power Self-Resetting Logic Design Approach

Volume 4 Issue 2 March - May 2016

Research Paper

An Optimized Low Power Self-Resetting Logic Design Approach

Shivani Kulshrestha*, Vikas Kumar Rai**
* PG Scholar, Department of Electronics and Communication Engineering, SIT, Mathura, U.P., India.
** Associate Professor, Department of Electronics and Communication Engineering, SIT, Mathura, U.P., India.
Kulshrestha, S., and Rai, V.K. (2016). An Optimized Low Power Self-Resetting Logic Design Approach. i-manager’s Journal on Circuits and Systems, 4(2), 17-21. https://doi.org/10.26634/jcir.4.2.8098

Abstract


This paper presents a new optimized technique to power reduction and performance improvement based on selfresetting logic. The concept of self-resetting logic uses the concept of resetting the output logic automatically after a certain time span. The proposed circuit eliminates the problems of SRLGDI logic proposed previously. SRLGDI was proven to be better than dynamic logic, CMOS self-resetting logic and GDI. Three designs of full adders were made using SRLGDI and a final proposed design was made using modified SRLGDI logic and compared to three SRLGDI designs to prove the performance improvement achieved using the modified SRLGDI logic.

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