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Configurable Double Precision Floating Point Multiplier For Error Tolerant Applications


Volume 3 Issue 1 December - February 2015
Research Paper
Configurable Double Precision Floating Point Multiplier For Error Tolerant Applications
K. Charan Kumar*, K. Neelima**
*-** Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.
Kumar, C. K., and Neelima, K. (2015). Configurable Double Precision Floating Point Multiplier For Error Tolerant Applications. i-manager’s Journal on Circuits and Systems, 3(1), 10-18. https://doi.org/10.26634/jcir.3.1.3258
Abstract
The floating point multiplier design is crucial for most applications like in GPUs. The designs are usually error prone. So the systems are developed to be error tolerant. The basic problem in floating point units is accuracy configuration. As accuracy plays a major role in many applications like rocket launches, the accuracy can be configured by using a log path rather than full path. Even though the error percentage increases in log path, the FP multiplier can be configured to have low power dissipation and area. The designs are developed using Verilog HDL and are functionally verified using ISIM simulator. The synthesis of the double Precision Multiplier is carried out in Xilinx ISE synthesizer and the results proved to be optimized in terms of delay and area.

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