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Design and Verification of RNS Adder forModuli-Set {2K -1, 2K, 2K +1}


Volume 3 Issue 1 December - February 2015
Research Paper
Design and Verification of RNS Adder forModuli-Set {2K -1, 2K, 2K +1}
Praise Amulya*, K. Neelima**
* PG Student, VLSI, Sree Vidyanikethan Engineering College, Tirupati, Chittoor, A.P, India.
** Assistant Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupathi, Chittoor, A.P, India.
Amulya, C. P., and Neelima, K. (2015). Design and Verification Of RNS Adder For Moduli-Set {2K -1, 2K, 2K +1}. i-manager’s Journal on Circuits and Systems, 3(1), 5-9. https://doi.org/10.26634/jcir.3.1.3257
Abstract
RNS based adder circuit provides an efficient way, alternate to the conventional method due to its parallel operation and small data size. The main aim for improving the performance of computation of adder is that to eliminate the carry propagation chain which is time consuming. The integers are represented in its residues of particular moduli set. The adder depends on only residues of respective moduli set. This paper presents the design of adder which is capable of providing carry free operation with proposed design of forward converter and Compressor based RNS to Binary reverse    converter for the {2k -1, 2k , 2k+1}moduli set.

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