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Design Of A Low Power And Highly Stable Single Ended SRAM Cell


Volume 3 Issue 1 December - February 2015
Research Paper
Design Of A Low Power And Highly Stable Single Ended SRAM Cell
K. Neelima*, 
* M.Tech Student, Department of ECE, Siddartha Educational Academy Group of Institutions, Chinthagunta (V), Near C.Gollapalli, Tirupati .
** Assistant Professor, Department of ECE,Siddartha Educational Academy Group of Institutions, Chinthagunta (V), Near C.Gollapall , Tirupati.
Neelima, K. and Prasad, K. P. (2015). Design of a Low Power And Highly Stable Single Ended SRAM Cell. i-manager’s Journal on Circuits and Systems, 3(1), 28-34. https://doi.org/10.26634/jcir.3.1.3260
Abstract
As the area is shrinking with the scaling of technology, the design of SRAM memory with less leakage power becomes essential for portable devices. Due to the second order effects, the leakage power dominates the static and dynamic power at deep submicron technology. Inspite of applying low power techniques like multi-threshold logic, body biasing techniques, stacked structures etc, the existing SRAM designs at submicron region dissipate more power and become instable. This paper concentrates on low power highly stable single ended SRAM cell design using only seven transistors using Lector and Galeor based low power Techniques. Digital Schematic Tool is used to develop schematics. Microwind Tool is used to develop Layouts at different nanometer technologies. The designs are optimized for low power and good static noise margin. Also the designs are compared for submicron technologies downline from 180nm to 90nm.


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