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Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology


Volume 4 Issue 1 December - February 2016 

Research Paper

Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology

K. Rajesh*, K. Neelima**
* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.
** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.
Rajesh, K., and Neelima, K. (2016). Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology. i-manager’s Journal on Circuits and Systems, 4(1), 12-15. https://doi.org/10.26634/jcir.4.1.6030

Abstract

In modern CMOS technology, the growing demand of low cost integrated circuit requires RFICs featuring low power consumption, high level integration and high data rates, have become critical in wireless systems at around 10 GHz for emerging applications. By employing silicon-based technology it is possible to design low cost direct conversion receivers targeted at 8 - 40 GHz frequency bands. The main focus is on the design and implementation of a receiver front-end for Ka - band (27 - 40 GHz) applications. The drawbacks of these designs are LO self-mixing and 1/f noise. To overcome these drawbacks, a dual - band receiver is proposed to be designed by adopting a wideband two stage LNA and wideband mixer in a 0.18 μm Bipolar Technology. To suppress the LO self-mixing problems, the sub harmonic mixer is applied to the receiver and by adopting a 3D inductor, IF 3-dB bandwidth can be improved. The designs are modeled in SPICE and verified in HSPICE Synopsys tools.

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