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FPGA Implementation Of Barrel Shifter using Reversible Logic


Volume 2 Issue 1 December - February 2014
Research Paper
FPGA Implementation Of Barrel Shifter using Reversible Logic
S. Justin Alex*, T. Antony Beno Prakash**, R. Anandarasu***, S. Poorna Lekha****, Komala Vani Chala*****
* -*** Final Year Electronics and Communications Engineering, V V College of Engineering.
****, ***** Assistant Professor, Department of Electronics and Communication Engineering, V V College of Engineering
Alex, S. J., Prakash, T. A. B., Anandarasu, R., Lekha, S. P and Chala, K. V. (2014). FPGA Implementation of Barrel Shifter using Reversible Logic. i-manager’s Journal on Circuits and Systems, 2(1), 28-33. https://doi.org/10.26634/jcir.2.1.2786
Abstract
Conventional Combinational logic circuits dissipate heat for every bit of information that is lost during their operation. Due to this fact the information once lost cannot be recovered in any way. A reversible logic gate is a n-input, n-output logic device which helps to determine the outputs from the inputs but also the inputs can be recovered from the outputs. Extra inputs or outputs are added so that the number of inputs is made equal to the number of outputs whenever it is necessary. For reversible computer the heat dissipation is logically 0. Therefore, in upcoming high performance it is considered as the promising technology at low power consumption. Therefore, there is requirement of designing reversible gates. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. The proposed techniques overcome the shortcoming of the present techniques like garbage output, delay and quantum cost and efficiency in designing the circuit which can be performed effectively by increasing the performance and reducing the delays with the same power consumption. It also reduces the no of flip flops, and gates which reduces the memory size and area.

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