Skip to main content

Implementation Of Pipelining for Modified Fused Multiply Add Architecture


Volume 2 Issue 4 September - November 2014
Research Paper
Implementation Of Pipelining for Modified Fused Multiply Add Architecture
Duvvuru Praveen Kumar*, M. Bharathi**
* M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.
** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.
Kumar, D. P., and Bharathi, M. (2014). Implementation Of Pipelining for Modified Fused Multiply Add Architecture. i-manager’s Journal on Circuits and Systems, 2(4), 7-12. https://doi.org/10.26634/jcir.2.4.3219
Abstract
Fused Multiply Add (FMA) units generally reduce delay in the overall circuit and also make it efficient in terms of energy in arithmetic operations. In this paper, the authors present an effective implementation of MFMA (Modified FMA) using pipelining by decreasing the delay compared to the parallel processing of the module. This MFMA uses two desperate Massif which are connected using pipelining. The final operation performed is A*B+C*D+F*G+H*I, parallel processing just implements unto A*B+C*D. The clock limiting stage for both these operations is involved in normalization stage and rounding stage. This paper is related to floating point calculations. Floating point calculations involve, a standard format for representing floating point numbers. The standard format for representing floating point numbers is IEEE 754- 2008.This floating point representation is used here. In this paper the pipelining implementation is mainly related to speed, i.e., delay of the circuit. This paper can be designed using trilogy HDL or VHDL and is simulated and synthesized in XILINX ISE 10.1 of FPGA.

Comments

Post a Comment

Popular posts from this blog

An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive

Volume 2 Issue 1 December - February 2014 Research Paper An improved Multilevel Inverter with Lesser Number of Switches for An Induction Motor Drive Ayyappa Srinivasan M G*, Nirmal Singh** *Assistant Professor, Department of Electrical and Electronics Engineering, St.Mother Theresa Engineering College, Tuticorin, India. **Professor, Department of Electronics and Communication Engineering, V.V. College of Engineering, Tisayanvilai, India Srinivasan, A.M.G and Singh, N. N (2014). An Improved Multilevel Inverter With Lesser Number of Switches for an Induction Motor Drive.  i-manager’s Journal on Circuits and Systems , 2(1), 7-14.  https://doi.org/10.26634/jcir.2.1.2783 Abstract An improved three level inverter scheme, with less number of switches, having the features of common mode voltage elimination, DC link capacitor voltage balancing, and minimization and equalization of voltage stress across the switches, for an open end winding induction motor drive, h...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer

Volume 1 Issue 1 December - February 2013 Research Paper Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer S.Padmini*, Subransu Sekhar Dash**, S. Chandrasekhar***, Priyanka Vedula**** * Assistant Professor, SRM University. ** Professor and Head, Department of EEE, SRM University, Shruti. ***-**** B. Tech Student, SRM University. Padmini, S., Dash, S. S., Chandrasekhar, S. and Vedula, P. (2013). Fuzzy Logiccontrol Of Differential Protection For Large Power Transformer.  i-manager’s Journal on Circuits and Systems , 1(1), 10-15.  https://doi.org/10.26634/jcir.1.1.2194 Abstract Advances Differential prot ecti on system is us e d t o protect most of the power transformers in power systems. The protection system is based on the differential currents/voltages of the primary an d secondary of the transformers under fault conditions and under normal operating conditions. The inrus currents or the magnetizing currents are generated in the...
Post a Comment
Read more