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Performance Analysis of Various Techniques on 6T SRAM Cell


Volume 3 Issue 2 March - May 2015
Review Paper
Performance Analysis of Various Techniques on 6T SRAM Cell
Pushpa Raikwal*, Vaibhav Neema**, Ajay Verma***
*_** Assistant Professor, Electronics & Telecommunication Engineering Department, Institute of Engineering & Technology, Devi Ahilya University, Indore, India.
*** Professor and HOD, Electronics & Instrumentation Engineering Department, Institute of Engineering & Technology, Devi Ahilya University, Indore, India.
Raikwal, P., Neema, V., and Verma, A. (2015). Performance Analysis of Various Techniques on 6t SRAM Cell. i-manager’s Journal on Circuits and Systems, 3(2), 29-34. https://doi.org/10.26634/jcir.3.2.3413
Abstract
Leakage current has been a major issue in system on chip designs with sub-micron technologies. For 180nm and below technologies, leakage is the main factor which dominates over the dynamic power and contributes to almost or more than 40% of total power dissipation. Thus it become very important to control the leakage current. This paper presents the effect of several techniques based on leakage reduction mechanism such as stacking effect and sleepy stack transistors on standard 6-T SRAM cell. Also their comparative analysis has been carried out on the basis of leakage current, propagation delay, static noise margin (SNM) and dynamic power dissipation. The produced result depicts SRAM cell with stack technique shows 16.65%increase in propagation delay, whereas sleepy stack SRAM shows 32.83% reduction in delay as compare to basic 6T SRAM cell. When we discuss about dynamic power dissipation 6T SRAM cell with stack technique consumes 39% more, but sleepy stack cell(in sleep mode) dissipates 17.61% reduced and sleepy stack cell (in active mode)dissipates 10.47% less power as compare to basic 6T SRAM cell.
About leakage current, it can be seen that 6T SRAM cell with stacking effect shows 86% less leakage flowing through the NMOS transistor whereas in PMOS transistor the leakage current got reduced to 99.94% as compare to basic 6T SRAM cell. When we come to sleepy stack technique the leakage current flowing through the NMOS cell increases by 111%, where there is a small difference in leakage of PMOS as compare to leakage of PMOS of 6T SRAM cell. Tools Used: TANNER EDA for schematic simulation, The simulation technology used is TSMC 180nm.

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