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Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme


Volume 1 Issue 1 December - February 2013
Research Paper
Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme
A. Saisudheer*, V. Muralipraveen**
* M.Tech, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.
** Assistant Professor, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.
Saisudheer, A. and Muralipraveen, V. (2013). Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme. i-manager’s Journal on Circuits and Systems, 1(1), 16-21. https://doi.org/10.26634/jcir.1.1.2195
Abstract
In this paper, a low-power pulse-triggered flip-flop (FF) designed and a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52

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