Skip to main content

Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme


Volume 1 Issue 1 December - February 2013
Research Paper
Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme
A. Saisudheer*, V. Muralipraveen**
* M.Tech, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.
** Assistant Professor, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.
Saisudheer, A. and Muralipraveen, V. (2013). Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme. i-manager’s Journal on Circuits and Systems, 1(1), 16-21. https://doi.org/10.26634/jcir.1.1.2195
Abstract
In this paper, a low-power pulse-triggered flip-flop (FF) designed and a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52

Comments

Post a Comment

Popular posts from this blog

Continuous Overvoltage Characteristics of Surge Protected Power Strips

Volume 5 Issue 4 September - November 2017 Research Paper Continuous Overvoltage Characteristics of Surge Protected Power Strips Cengiz Polat* Assistant Professor, Department of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey. Uzunoglu, C. P. (2017). Continuous Over Voltage Characteristics of Surge Protected Power Strips.  i-manager’s Journal on Circuits and Systems,  5(4), 1-7.  https://doi.org/10.26634/jcir.5.4.13938 Abstract Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) ...
Post a Comment
Read more

Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Volume 1 Issue 4 September - November 2013 Research Paper Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop M.Karthick*, S. Vijayakumar** *PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. **Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India. Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop.  i-manager’s Journal on Circuits and Systems , 1(4), 22-26.  https://doi.org/10.26634/jcir.1.4.2593 Abstract Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is p...
Post a Comment
Read more

A Review on Control strategies for LFC in Deregulated Scenario

Volume 1 Issue 1 December - February 2013 Review Paper A Review on Control strategies for LFC in Deregulated Scenario T. Anilkumar*, N. Venkata ramana** * Associate Professor, EEE Department, ACE Engineering College, Ghatkesar, Hyderabad, AP, India. ** Professor and Head of Deportment, EEE Department, JNTU Mantini, AP, India. Kumar, T. A., and Ramana, N., (2013). A Review On Control Strategies For LFC In Deregulated Scenario.  i-manager’s Journal on Circuits and Systems , 1(1), 27-36.  https://doi.org/10.26634/jcir.1.1.2197 Abstract In power system studies, Load frequency control is an important issue to supply sufficient and reliable electric power with good quality. The main objective of LFC is to maintain load frequency and tie-line power flow within permissible limits by adjusting megawatt output of LFC generators, so as to accommodate fluctuating load demands. This paper presents a brief review of different control techniques to researchers on design...
Post a Comment
Read more