Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

Volume 1 Issue 4 September - November 2013

Research Paper

Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

Vanitha*, M. Parimaladevi**, D. Sharmila***

*PG Scholar, Department of ECE, Velalar College of Engineering and Technology, Erode.

**Assistant Professor, Department of ECE, Velalar College of Engineering and Technology, Erode.

*** Professor/Head, Department of EIE, Bannari Amman Institute of Technology, Erode.

Vanitha, P., Parimaladevi, M., and Sharmila, D. (2013). Subthreshold Leakage Reduction Strategies for the Design of Low Power SRAM. i-manager’s Journal on Circuits and Systems, 1(4), 6-13. https://doi.org/10.26634/jcir.1.4.2590

Abstract

The intensifying trade of transportable electronic devices such as cell phones, laptops, tablet PCs and other handheld devices require minimum power dissipation for retaining the battery life, high reliability and compactness of the system. The highly energy efficient processors and handheld portable systems involve SRAMs as the crucial components which indicate that significant notice has to be given in designing the high performance and power reduced SRAMs. The consumption of power and area penalty of SRAM(Static Random Access Memory) reaches a higher value accordingly with the scaling down of technology. This Paper mainly deals with the subthreshold leakage current which is the predominant leakage component of SRAM cell and circuit level leakage reduction techniques to obtain subthreshold leakage reduced SRAM cell. Various SRAM cell topologies are summarized in the point of subthreshold leakage reduction and their subthreshold and gate leakage currents Hold SNM at various temperatures and process the corners which have been measured and compared. Simulations are performed with 90nm CMOS technology process file using Mentor Graphics. Finally, the 8T SRAM bitcell has been identified as the best cell topology designed with dynamic V DD scaling technique, which reports considerable leakage reduction over 6T at all process corners. Simulation results revealed that there is a considerable improvement of hold SNM at 25ºC in 8T over other SRAM cell topologies.