Skip to main content

Comparative Study of Modelling Techniques for Transformerless Three Phase NPC Inverter to Eliminate Harmonic in PV System

Volume 4 Issue 3 June - August 2016

Research Paper

Comparative Study of Modelling Techniques for Transformerless Three Phase NPC Inverter to Eliminate Harmonic in PV System

Romi Choudhary*, A.N. Tiwari**
* PG Scholar, Department of Electrical Engineering, MMMUT, Gorakhpur, Uttar Pradesh, India.
** Associate Professor, Department of Electrical Engineering, MMMUT, Gorakhpur, Uttar Pradesh, India.
Choudhary, R., and Tiwari, A.N. (2016). Comparative Study of Modelling Techniques for Transformerless Three Phase NPC Inverter to Eliminate Harmonic in PV System. i-manager’s Journal on Circuits and Systems, 4(3), 15-23.https://doi.org/10.26634/jcir.4.3.8220

Abstract


The main objective of this paper is the proposal of new modulation techniques for three phase transformerless neutral point clamped inverters to eliminate harmonics in photovoltaic systems without requiring any modification on the multilevel inverter or any additional hardware. The modulation techniques are capable of reducing the harmonics in photovoltaic systems by applying PWM (Pulse Width Modulation) and SVPWM (Space Vector Pulse Width Modulation) or converter. A multilevel power conversion concept is based on the combination of Neutral-Point -Clamped (NPC) and floating capacitor converters. In the proposed scheme, the voltage balancing across the floating capacitors is achieved by using a proper selection of redundant switching states, the input source is PV System. The output voltage waveforms in neutral point clamped inverters can be generated at low switching frequency losses with high efficiency and low distortions. This paper presents the switching pattern to generate symmetrical gating signal to control NPCVSI (Neutral Point Clamp Voltage Source Inverter) using matlab/simulink.

Comments

Post a Comment

Popular posts from this blog

Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level

Volume 1 Issue 2 March - May 2013 Research Paper Fuzzy Based Power Quality Improvement In Grid Connected Microgrid At The Distribution Level Naveen Bolisetti*, Mothiram Bhukya** * Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. ** Department of Electrical and Electronics Engineering, SRKR Engineering college, Bhimavaram, Andhra Pradesh, INDIA. Bolisetti, N., and Ram, M. B. (2013). Fuzzy Based Power Quality Improvement In Grid Connected Microgrid at the Distribution Level.  i-manager’s Journal on Circuits and Systems , 1(2), 1-6.  https://doi.org/10.26634/jcir.1.2.2288 Abstract This paper suggests a new control strategy that consists of a grid interfaced four leg inverter control system using adaptive fuzzy controller for a 3-phase 4-wire distribution system that is capable of simultaneously compensating problems like power factor, current imbalance and current harmonics, and also of inject...
Post a Comment
Read more

Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs

Volume 5 Issue 4 September - November 2017 Research Paper Design and Implementation of Low Power ALU Using 8T Full Adder with FinFETs M. Chandra Sekhar Reddy*, P. Ramana Reddy** * Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapuramu, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India. Reddy, M. C. S., and Reddy, P. R. (2017). Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS.  i-manager’s Journal on Circuits and Systems , 5(4), 8-14.  https://doi.org/10.26634/jcir.5.4.13939 Abstract An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ...
Post a Comment
Read more

Power Efficient Functional Units for High Speed Computations

Research Paper Power Efficient Functional Units for High Speed Computations B. Dinesh*, R. Jagadeesh**, M. Kathirvelu*** *,** PG Students, Department of ECE, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India. *** HOD & Professor, Department of Electronics and Communication, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu. Dinesh, B. Jagadeesh, R. and Kathirvelu, M. (2013). Power Efficient Functional Units For High Speed Computations.  i-manager’s Journal on Circuits and Systems , 1(3), 13-18.  https://doi.org/10.26634/jcir.1.3.2443 Abstract Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times ar...
Post a Comment
Read more